Circuit and method of erasing a nonvolatile semiconductor memory

摘要

A system capable of stabilizing a tight distribution of threshold voltages of erased flash EEPROM memory cells within a fast time period includes at least one memory cell having source, channel and drain regions on a semiconductor substrate, a floating gate over the channel region on a tunnel oxide layer and a control gate over the floating gate, and a circuit for converging the threshold voltage of an erased memory cell to within a predetermined voltage range. The circuit includes: a driving circuit for applying a first voltage to the control gate and a second voltage between the source and drain regions during the self-convergence operation; and a backbias generator for applying a backbias voltage to the substrate so as to generate hot electrons/holes in the channel region and to inject ones of the hot electrons/holes into the floating gate during the self-convergence operation.