| 摘要 |
1470376 Automatic control of battery voltage ELECTRIC POWER STORAGE Ltd 5 July 1974 [9 July 1973] 32572/73 Heading G3N and G3R [Also in Division H2] In a battery charging system, the charging current is automatically adjusted so that the battery voltage approaches a reference voltage. The reference voltage is progressively increased during a phase of the charging cycle by a circuit including a pulse generator, a counter and a digital-to-analog converter. In the system described, charge current initially builds up slowly over a period of three minutes and continues until a voltage of 2.36 volts per cell, for a lead acid battery, is reached. Subsequently, the reference voltage is progressively increased and the charge current controlled so that cell voltage increases at up to 0.1 volts per hour. The current gradually decreases until a point is reached where the current begins to increase in order to try to maintain the rate of voltage increase. This minimum current point is detected, and the first phase of the charge cycle is terminated. If no minimum has been reached after a pre-set time, phase one is similarly terminated. During the succeeding phase two, the battery is charged in pulses each of which is triggered when the battery voltage falls to say 2.18 volts per cell. Pulse current is arranged to increase gradually to the maximum available. A pulse is ended either when the battery reaches the value attained at the end of phase one or after a predetermined time, say four minutes. In Fig. 1, a battery is charged from a three-phase supply over a thyristor bridge 201 including ballast chokes and surge suppressors, Fig. 2 (not shown) and phase controlled by a firing circuit III, Fig. 3 (not shown), of ramp and pedestal comparison type and using slave thyristors for producing firing signals for the thyristor bridge 201. The pedestal voltage generator IV, Fig. 4 (not shown), includes NOR and NAND gates and an FET circuit, and the amplitude of the pedestal voltage is determined by an output 61 from voltage control circuit V, Fig. 5 (not shown). This circuit includes a voltage comparator 503 receiving a reference input from a D-A converter 502 responsive to a binary counter 501 and a variable frequency oscillator 504 using a PUT circuit. A minimum current detector circuit VI, Fig. 6 (not shown), includes a current sensor and frequency converter 601 feeding a bi-directional counter 602 which counts upwards for a first sampling period and downwards for a second sampling period of slightly shorter duration, so that the counter returns to zero only when the charge current has begun to increase. A zero detector logic gate 605 initiates a logic section VII, Fig. 7 (not shown), to control the pulsed charging during phase two of the cycle. |
