| 摘要 |
A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH operation. The microprocessor (10) includes a floating-point unit (FPU) (31) having a register stack (52ST) and a stack pointer (FSP), for executing floating-point instructions containing relative register addresses (REG) based upon the contents (TOP) of the stack pointer (FSP). The instructions may involve PUSH operations, in which an operand is added to the stack of operands in the register stack (52ST). Register addressing circuitry (125, 125') includes an adder (122; 122') for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction, and an adder/decrementer (120) for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction minus one, to account for the PUSH. The adder (122; 122') and adder/decrementer (120) have their outputs coupled to a multiplexer (124) which is controlled according to whether or not the current instruction involves a PUSH operation. For the case where the contents (TOP) of the stack pointer (FSP) and the relative register address (REG), as well as the raw calculated register address, are each three-bit binary values, the adder/decrementer (120) may be constructed to perform the addition and subtraction of one with a single carry/borrow propagate add. |
