| 摘要 |
The coder (100) comprises a data register (15) receiving a stream of data signals from the data bus, and a control logic circuit (16) coupled to the data register, a system clock (CLK), and an output of the hardware bit coder. A programmable device defines signal patterns, which are coupled to a bit with high value and one with low value from data of the stream of data signals. The device is incorporated between the data bus and the control logic circuit. The data are loaded into the device. Each bit with low value is coded with a corresponding first selectable bit pattern, while each bit with high value is coded with a second pattern of bits. An Independent claim for a data coding method is included. |
