METHOD AND APPARATUS FOR LOW JITTER CLOCK RECOVERY

摘要

A method and apparatus is described for reducing jitter in data sample clock rates recovered from isochronous streams of data packets having associated time stamp values, such as in an IEEE 1394 bus-interconnected system. Jitter associated with variations in the free running quartz-driven PHY clocks is reduced by instead driving local PHY clocks with a phase-locked loop circuit referenced to the Link cycle-out pin, which toggles when the cycle time register cycle-offset field wraps and the cycle-count field increments. Because the cycle-out pin toggles at a frequency proportional to the cycle master's PHY clock, jitter associated with local PHY clock variations is reduced. Jitter associated with quatization noise from finite length time stamp generation is reduced by dithering and noise shape filtering conventional time stamps. This decorrelates the jitter and shifts the associated noise out of the expected frequency band of the sample clock sign al to be recovered.