发明名称 SYSTEM AND METHOD FOR IDENTIFYING FINITE STATE MACHINES AND VERIFYING CIRCUIT DESIGNS
摘要 To identify a finite state machine and verify a circuit design, the invention identifies, in a design description, a set of constructs (602), a construct in the set of constructs (604), and an object in the construct (606). It next identifies a first subset of constructs in the set of constructs which can control a change of a value of the object (608), and then identifies a second subset of constructs whose values can be changed directly or indirectly by the object (610). The identifying and storing steps are repeated for all objects in the construct and for all constructs in the set of constructs (612-614). A finite state machine is identified by searching for a first object which controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object (616). This method of identifying finite state machine elements in a design description is used by a test generator which then generates test vectors for exercising the finite state machine elements on a test bench (618-626).
申请公布号 WO9959079(A1) 申请公布日期 1999.11.18
申请号 WO1999US09460 申请日期 1999.04.30
申请人 SUREFIRE VERIFICATION, INC. 发明人 MCNAMARA, MICHAEL;TAN, CHONG;CHIEN, CHIAHON;MASSEY, DAVID
分类号 G01R31/28;G01R31/317;G01R31/3183;G06F11/26;G06F11/263;G06F17/50;(IPC1-7):G06F17/00 主分类号 G01R31/28
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