| 摘要 |
<p>A full programmable and erasable non-volatile floating gate memory array (70) of rows (86) and columns (26). Each cell (10) is of the type with a first region, a spaced apart second region and a channel region in between. A floating gate is disposed over and is insulated from a portion of the channel region and the second region. An electrically conductive gate has a first section disposed over and insulated from the first region and is disposed and is adjacent to the floating gate and is insulated therefrom and has a second section disposed over the floating gate and is insulated therefrom. The array has a plurality of first transistors interposed in each row for connecting the second regions of the memory cells arranged in each row to the common line. Each of the plurality of first transistors has an associated first portion of the memory cells in each row.</p> |
