| 摘要 |
A high speed digital to analog converter (DAC) includes an integrator formed with an operational amplifier (OP1), a first capacitor (C1), and a resistance (R1). In this circuit a pulse width modulated (PWM) signal is integrated to form an integrator voltage relative to a given reference voltage (Uref). Second and third capacitors (C2,C3) are used such that the second capacitor (C2) is charged to the output voltage of the integrator (OP1) during a first clock period (to-t3,t3-t6) of the PWM signal. The third capacitor (C3) is held constant at the voltage applied to it at the start (t0,t3) of the first clock period. This is used as the output signal of the DAC. During a second clock period, the third capacitor is charged to the output voltage of the integrator (OP1), and the second capacitor (C2) is held constant at the voltage applied to it at the start of the second clock period.
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