| 摘要 |
<p>The degree of complexity of the signal connection relationship of a logic circuit is taken into consideration to improve the precision with which layout area is estimated, thereby making it possible to implement layout and wiring with the minimum required development time and without unwired portions being left in the layout area. Processing includes (S1) inputting connection information relating to a logic circuit; (S2) allocating the number of logic stages of each logic cell; creating data which is a combination of node name, pin attribute, logic cell name and number of logic stages in regard to each pin of the logic cell; (S3) calculating a variance in the overall number of input pins classified by number of logic stages; (S4) calculating a parameter relating to the difference between the number of logic stages of an output pin and the number of logic stages of an input pin; (S5) calculating a parameter relating to the overall number of connected pins of each logic cell; evaluating a calculation equation for estimating layout area from the calculated variance and calculated parameters; and estimating layout area. <IMAGE></p> |
