| 摘要 |
A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, (e.g., 77 or 101) illustratively, having a dopant, dye, etc. termed a "marker layer" is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer (e.g., 103) is deposited upon the marker layer. The undoped or undyed layer (e.g., 103) is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated. Alternatively, the material layer (e.g., 77 or 101) is formed on an undoped or undyed dielectric layer (e.g., 61 or 75). |
