| 摘要 |
A plurality of modules, each connected to communication lines, are interconnected by a logically separated interprocessor communication bus for transferring header information and control information and a frame transfer bus for transferring data. When each module receives data from a line, the module generates a header containing header information from the received data, stores the header and user data in respective queue-type data storage sections, and transmits the header on the interprocessor communication bus; when one of the other modules detects its own identification from the header on the bus, the module sends a data send request to the transmitting module which in response reads the data from the data storage and outputs it on the frame transfer bus for transmission to the requesting module.
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