Microprocessor system with flexible instruction controlled by prior instruction

摘要

A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing instructions. At least some of the instructions have an immediate data format including a field for intermediate data and a field for specifying a destination for an output. The ALU uses two operands for performing at least some of the instructions having the immediate data format. The ALU conditionally accepts either the contents of the input pipeline latch or the ALU output of the previous instruction as a second operand to an immediate instruction depending on the destination specified in the destination field of the previous instruction.