| 摘要 |
A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit. The delay circuit serves to obtain a desired delay time by varying a control voltage irrespective of unstable time delay values of components caused by the fabrication process.
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