| 摘要 |
PURPOSE:To reduce the occupying area of a connection forming region in an integrated circuit including many C-MOS inverters by symmetrically disposing an N channel MOST and a P channel MOST between the external connection forming regions, thereby eliminating a parasitic effect. CONSTITUTION:Input/output circuit forming region 3 is formed between external connection forming regions 2 and 4. In the region 3, the A13, A12, A11 of an N channel MOS and A21, A22, A23 of a P channel MOS are sequentially formed in this sequence. A C-MOS inverter is composed with the A13, A23; A12, A22; and A11, A21 of the MOS. In this manner, the occupying area can be reduced while eliminating the production of the parasitic thyristor effect, and the pad area for external connection can be also reduced, thereby performing high integration. |
