发明名称 |
Semiconductor storage device |
摘要 |
Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN0-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks. <IMAGE> |
申请公布号 |
AU3344999(A) |
申请公布日期 |
1999.11.08 |
申请号 |
AU19990033449 |
申请日期 |
1999.04.20 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
HIRONORI AKAMATSU;TORU IWATA;MAKOTO KOJIMA |
分类号 |
G11C8/12;G11C8/14;G11C11/408 |
主分类号 |
G11C8/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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