| 摘要 |
PURPOSE:To reduce a peak current and VDD noises by precharging a bit line potential separately in three stages with regard to the bit line precharging system of an MOS semiconductor storage device. CONSTITUTION:A clock phiP1 rises from the ground potential to a potential (VDD- (thershold voltage of transistor Q33)) as a clock phi1 rises in potential. Then, a clock phi2 rises in potential and the gate potential of a TRQ32 drops to the ground potential to boot up the potential at a node N3 above the VDD depending upon the capacity ratio of the TRs Q31 and Q32, thereby holding the phiP1 at the potential VDD. Then, the potential of a clock phi4 rises to hold the node N3 at the ground potential and the phiP1 is booted up above the VDD by boot-up capacitance C3. The phiP1 is stopped temporarily at the 1st potential, i.e. (VDD- (threshold voltage of Q33)) and the potential difference between the phiP1 and bit line is stopped at a value smaller than before. Therefore, a peak curren is controlled without extending the potential rise time of the phiP1. |
