| 摘要 |
PURPOSE:To perform stable operation even when delay (skew) between a clock and an inverted clock signal increases by adding an extremely simple circuit to a CMIS static RAM which performs clock operation. CONSTITUTION:A transistor (TR) 2 is connected to a write word line WL and the clock signal CK is inputted to its gate. Consequently, the inverted clock signal -CK lags behind the clock signal CK, and the TR2, therefore, turns on to hold the write word line WL at a level L when the clock signal CK goes up to a level H even when a signal WE.CK lags, so writing is not performed even when a gate in a memory cell MC turns on. Thus, the RAM operates stably even when the difference between the clock signal CK and inverted clock signal -CK increases. |
