发明名称 METHOD AND CIRCUIT FOR REDUCING NOISE OF PLL OSCILLATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method/circuit for reducing the harmonic noise of an oscillation circuit. SOLUTION: A lock detector 8 detecting a lock state from the output of a phase comparator 5, a D-flip flop 9 outputting a high level signal from a lock detection signal D being the detecting signal, a clock TnQ and the starting control signal PS of PLL and a current source 10 stopping current to an oscillation circuit 7 to which the high level signal is inputted are provided. The oscillation circuit 7 sets the negative resistance |-Rn| of the circuit to a high gm value which is 3-10 times as much as the equivalent resistance Re of a crystal oscillator at the time of starting. When current from the current source 10 is stopped, the gm value is reduced as |-Rn|=Re. Thus, the occurrence of harmonics is suppressed and noise is reduced.
申请公布号 JPH11308103(A) 申请公布日期 1999.11.05
申请号 JP19980107740 申请日期 1998.04.17
申请人 NEC CORP 发明人 YOSHIOKA KENJI
分类号 H03B5/32;H03L7/08;H03L7/10;H03L7/18 主分类号 H03B5/32
代理机构 代理人
主权项
地址