| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which high speed operation is performed with low power consumption while limiting the chip area. SOLUTION: The semiconductor memory comprises load circuits 20.0,... of column sense amplifiers arranged in correspondence with Y address (global bit pair line). A plurality of memory blocks BK0,... share the load circuit 20. Each memory block is provided with the input circuits 10.0,... of column sense amplifiers for each pair of bit lines. The input circuits 10.0,... are activated in response to a corresponding block select signal. In response to the potential of corresponding pair of bit lines, potential difference of corresponding pair of global bit lines appears. The load circuits 20.0,... widen the potential difference. |
