发明名称 BIT SYNCHRONIZATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a data output synchronizing with a system clock from an inputted burst signal without the use of an elastic buffer or the like. SOLUTION: A signal sampling section 10 samples an inputted burst signal in a multiphase clock to generate multiphase data streams. A change point detection section 20 detects a change point of the burst signal by comparing adjacent phase data among the multiphase data streams. A clock selection section 30 selects an optimum identification clock that is optimum to identify the burst signal among the multiphase clocks based on the phase information detected by the change point detection section 20. A clock replacement section 40 applies processing to replace the burst signal to a system clock based on the optimum identification clock and the phase information.
申请公布号 JPH11308204(A) 申请公布日期 1999.11.05
申请号 JP19980108189 申请日期 1998.04.17
申请人 TOSHIBA CORP 发明人 NAKAO MASATOSHI;INAGAKI YOSHIO
分类号 H03K5/00;H04L7/02 主分类号 H03K5/00
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