| 摘要 |
PROBLEM TO BE SOLVED: To reduce overhead at the time of check point processing by realizing a high-speed cache flash. SOLUTION: A cache flash device 1 is equipped with a modified flag(MF) RAM 2 and a modified block table(MBT) RAM 3. The MBT Tag RAM 3 stores address information regarding the modified block of a cache of all the processors in each entry for each cache line. The MF RAM 2 stores data which have a value obtained by performing a logical sum with a modify bit for all the processors in each entry together with an index as information for retrieving the index of an entry which includes an address of at least one modified block out of each of entries on the MTB Tag RAM 3. At the time of cache flash, an address of the modified block can be read at high speed by using information stored in the MF RAM 2. |
