| 摘要 |
<p>PROBLEM TO BE SOLVED: To easily and effectively process both cache and DMA control requests by performing the cache control and the DMA control against the cache and DMA control requests shown by a decision signal respectively. SOLUTION: An address decoder part 21 supplies the control signals including addresses to a cache control part 22, a data memory part 24 and a data selection part 26 as the decision signals showing the decision results. The part 22 gives a request to the data of a cache memory part 23 if the address of an input request exists at the part 23 against the access given from the part 21. A DMA control part 25 occupies one of ports of the part 24 against the input request given from a processor part 1 and transfers the data received from a main storage part 3 to the part 24 or transfers the data received from the part 24 to the part 3. Thus, either the cache control or the DMA control is carried out when the decision signal shows the cache or DMA control requests.</p> |
