发明名称 INSULATION GATE TYPE SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce on-resistance from the relation ship between the junction depth of a base region against groove depth and the on-resistance. SOLUTION: When forming a groove 23 which penetrates a base region 26, the groove 23 is relative to the junction depth of the base region 26, formed by 0.15-0.50μm in depth, if the resistivity of a drain region is 4Ω-cm or less while formed by 0.3-1.0μm in depth if it is 4 to 8Ω-cm. A void layer, heading for the drain region 25, between the drain region 25 and the base region 26 when an MOSFET is on-operation state extends as deep as the groove 23, for no occurrence of resistance component due to apparent junction FET, and the resistance component between the groove 23 and the void layer comes to be the resistance component between an R-shaped corner part between the sidewall and the bottom of the groove 23 and the void layer, thus reducing the on-resistance of the MOSFET than before.
申请公布号 JPH11307767(A) 申请公布日期 1999.11.05
申请号 JP19980110006 申请日期 1998.04.21
申请人 NEC KANSAI LTD 发明人 MATSUURA NAOKI;UNO HIROHIKO
分类号 H01L29/78;(IPC1-7):H01L29/78 主分类号 H01L29/78
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