发明名称 DYNAMIC TYPE RAM
摘要 PROBLEM TO BE SOLVED: To reduce an exclusive area by a method wherein three sub-arrays are arranged to a word line direction, and complementary bit line pairs comprising 1024 collectively are divided so that each becomes substantially an equal number. SOLUTION: A sub-array 15 is formed so as to be enclosed with a sense amplifier region 16 and a sub-word driver region 17 across the sub-array 15. A memory chip 10 is provided with word lines of 8K to a bit line direction and bit line pairs of 8K to a word line direction, for example, and the entire has a memory capacity of about 64M bits. Complementary bit lines of 1K (1024 pairs) for arranging the sub-arrays 15 to a sub-array word line direction are substantially trisected. Alternatively, three sub-arrays 15 are arranged to a bit line direction and sub-word lines comprising 1024 lines altogether are distributed so that each becomes a substantially equal number. Thus, a time constant increases at most 1.7 times the case of 256 BL pairs and a reduction of a chip area can be contemplated.
申请公布号 JPH11307739(A) 申请公布日期 1999.11.05
申请号 JP19980108825 申请日期 1998.04.20
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 KATO SHIGENOBU;KITSUKAWA GORO;SAKURAI KIYOTAKE
分类号 G11C11/407;G11C11/401;H01L21/8242;H01L27/108 主分类号 G11C11/407
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