| 摘要 |
PROBLEM TO BE SOLVED: To impart error correction ability exceeding the limit of BCH code logic by inverting a bit for which an error is not detected from '0' to '1' and then performing an error detection/correction processing in the case that the bit error of the optional symbol of one phase is corrected, the bit of the same symbol of the other phase is '0' and the error is not detected. SOLUTION: A decoding part 13 extracts the data of the phase (a) and the phase (c) from a bit string developed to the array of 8×32 of a buffer memory at the time of 3200 bps for instance. Or, at the time of 6400 bps, the data of the phases (a), (b), (c) and (d) are extracted from the same bit string. In the stage, the judgement of BCH (31, 21) code + even-numbered parity is made possible. An error correction part 14 fetches the data for which demultiplexing is ended, performs a processing by known 2-bit error correction algorithm by a word unit, extracts an information bit and transfers it to a one-chip microcomputer 15.
|
