Device for delay of external clock signal in e.g. synchronous dynamic random access memory (SDRAM)

摘要

The device has a clock signal delay unit, which functions according to natural reception and energizing time delay. A pulse generator (12) receives a clock signal (eCLK) from a delay unit (11) and generates rectangular synchronous pulses with rising flanks. The generated pulse passes through a circular relay unit (13) with delay units in circular formation and is delayed. A signal from each unit is stored synchronously with the clock signal (rCLK) received by chip. The received clock signal is delayed by a first clock signal delay unit (20), while a second clock signal delay unit (21) provides fine delay of the signal from the first delay unit according to a latch signal from the circular delay unit. A resetting signal generator (22) completes the assembly.