发明名称 |
Metal staples to prevent interlayer delamination |
摘要 |
The present invention provides in one embodiment thereof an integrated circuit (IC) that includes silicon substrate. The integrated circuit includes a plurality of dielectric and metal layers formed upon the silicon substrate. The plurality of dielectric and metal layers form a die active area. The metal have formed therein a first guard wall surrounding the die active area. The metal layers further have formed therein a second segmented guard wall. The segmented guard wall surrounds and staples the plurality of metal layers. The IC also includes a passivation layer adhering to the first and the segmented guard walls. |
申请公布号 |
US5977639(A) |
申请公布日期 |
1999.11.02 |
申请号 |
US19970940304 |
申请日期 |
1997.09.30 |
申请人 |
INTEL CORPORATION |
发明人 |
SESHAN, KRISHNA;MIELKE, NEAL R. |
分类号 |
H01L23/31;H01L23/58;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L23/31 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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