| 摘要 |
Configurable logic circuit (10,110) and method may comprise a control circuit (12,112) and a logic circuit (14,114). The control circuit (12,112) may generate an intermediate clock function (36,136) in response to selection of one of a first (30,130) and a second (32,132) clock input based on a clock control input (34,134), generate a first control function (46,146) in response to selection of one of a first (40,140) and a second (42,142) control input based on the intermediate clock function (36,136) and generate a second control function (56,156) in response to selection of one of the second (42,142) and a third (52,152) control input based on the intermediate clock function (36,136). The logic circuit (14,114) may be coupled to the control circuit (12,112) and configured into one of a plurality of logic modes in response to a combination of the first (46,146) and second control functions (56,156).
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