发明名称 |
Low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistor |
摘要 |
The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction.
|
申请公布号 |
US5977572(A) |
申请公布日期 |
1999.11.02 |
申请号 |
US19970931087 |
申请日期 |
1997.09.15 |
申请人 |
NATIONAL SCIENCE COUNCIL |
发明人 |
LIU, WEN-CHAU;LOUR, WEN-SHIUNG;TSAI, JUNG-HUI |
分类号 |
H01L29/737;(IPC1-7):H01L29/737 |
主分类号 |
H01L29/737 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|