发明名称 |
Gate array LSI |
摘要 |
The present invention relates to the improvement in the degree of on-chip integration of memory cells utilizing a gate array layout. A plurality of three-transistor DRAM cells are disposed on a semiconductor chip implementing a regular cross-point array, each DRAM cell is made up of two nMOS transistors and one pMOS transistor formed in one basic cell. The semiconductor chip disposes therein nMOS memory-cell blocks and pMOS memory-cell blocks alternately, effectively utilizing the gate array layout.
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申请公布号 |
US5978301(A) |
申请公布日期 |
1999.11.02 |
申请号 |
US19970922024 |
申请日期 |
1997.09.02 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MAENO, MUNEAKI;UCHINO, YUKINORI;TANAKA, YUTAKA |
分类号 |
G11C11/405;H01L21/82;H01L21/8242;H01L27/10;H01L27/105;H01L27/108;H01L27/118;(IPC1-7):H01L27/10 |
主分类号 |
G11C11/405 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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