Method of making a self-aligned disposable gate electrode for advanced CMOS design

摘要

A method of fabricating an integrated circuit transistor in a substrate is provided wherein a self-aligned gate electrode is formed after the high temperature steps associated with sidewall spacer formation and source/drain anneal. A first dielectric layer is formed on a substrate. First and second source/drain regions are formed in the substrate and spaced laterally to define a channel region underlying the first dielectric layer. A second dielectric layer is formed on the substrate except where the first dielectric layer is positioned. The first dielectric layer is removed and a third dielectric layer is formed that overlies the channel region. A gate electrode is formed on the third dielectric layer. The first dielectric layer functions as a disposable gate electrode to facilitate self-aligned source/drain implant and sidewall spacer formation.