Built-in self-test in a plurality of stages controlled by a token passing network and method

摘要

This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC-RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC-RSs corresponding to one or more RSB elements into a matrix such that each SBRIC-RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC-RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC-RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.