| 摘要 |
PURPOSE:To approximately double the converting speed of resolution, through the resolution being n-1, by a method wherein, in a parallel type AD conversion LSI (large scale integrated circuit) having the resolution of n-bit digital output, a part of a mask is changed. CONSTITUTION:A clock wires G11, G12, G21, G22, G31, and G32 are individually connected to the control clock output, to be used for the n-1 bit of CG1. In this case, a group of comparators C1-C4-Cm/2 and latches SH1-SH4-SHm/2 and other group of comparators and latches are operated alternately. Besides reference voltage is generated by connecting an RV1 to an earthing conductor and an RV2 is connected to Vr1. Also, pertaining to an encoder, the timing of the encoder output is adjusted so that the encoder is is corresponded with an alternate operation. As a result, a comparative operation is performed on one side and then on the other side alternately, and the zero adjustment period of the comparator inflicts no effect on the processing time of an analogue signal, thereby enabling the titled integrated circuit device to perform a high speed operation.
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