Plate line driver circuit for a 1T/1C ferroelectric memory

摘要

A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.