| 摘要 |
A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal. Moreover, a second programmable delay means, connected between an output of the second logic gate and the second input terminal of the first logic gate, is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. The programmable non-overlap clock generator therefore generates a first clock signal from the output of the first logic gate, and generates a second clock signal from the output of the second logic gate, wherein the first clock signal and the second clock signal are not logically active at the same time.
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