| 摘要 |
PURPOSE:To set a test mode at a low test signal voltage level and to obtain a test input circuit suitable to high IC-implementation by lowering a source voltage and setting a test mode when a reset signal is generated. CONSTITUTION:When the reset signal S1 resets FFs 14 and 15 and the source voltage V reaches the detection level of a voltage detecting circuit 4, the circuit 4 detects the drop of the voltage V to generates an output H at a terminal 5 and an output L at the output terminal of an inverter 6, so an AND gate 7 does not pass the signal S1 when the output of the inverter 6 is H, so that an output S6 is L. Then when signals S2 and S3 of H corresponding to the test state are inputted to terminals 2 and 3, AND gates 9 and 10 pass the signals S2 and S3 to set the FFs 14 and 15, and when the signals S2 and S3 fall to L, pieces of information of the test signals S7 and S8 are held and the FFs 14 and 15 are inhibited from being reset. Consequently, the signals S2 and S3 are inputted to an internal circuit through AND gates 11 and 12 and a test is taken. |
