发明名称 PHASE LOCKED LOOP SYSTEM
摘要 PURPOSE:To prevent the undetection and misdetection of frame synchronization by applying phase locking with a PLL clock from a PLL circuit synchronously with a fixed clock for a prescribed period after the detection of a sector and a data read by an optical pickup after a prescribed period elapses. CONSTITUTION:The fixed clock from a fixed frequency oscillator 11 for a prescribed period after the detection of a sector being the object of retrieval and a PLL clock from the PLL circuit 5 synchronizing with an input data read from the optical pickup 2 after a prescribed period elapses are selected switchingly by a selector 13 by using a select signal from a counter 12 and the result is fed to a frame synchronization detection circuit 6. If a noise, a flow on the disk or disturbance of an output data of an optical system are caused at a time till the frame synchronization signal detected at first after the frame synchronizing detection circuit 6 is started by a sector detection flag, the frame synchronization detecting circuit 6 outputs a forecast function at a proper position to detect the frame synchronizing signal.
申请公布号 JPS62262277(A) 申请公布日期 1987.11.14
申请号 JP19860106049 申请日期 1986.05.09
申请人 RICOH CO LTD 发明人 SUZUKI MASAMITSU;YAMADA WASAKU
分类号 G11B20/14;H03L7/14 主分类号 G11B20/14
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