发明名称 WAFER PLANATARIZATION METHOD, WAFER PLANATARIZATION SYSTEM AND WAFER
摘要 PROBLEM TO BE SOLVED: To provide a wafer planatarization method which enables the high- accuracy planatarization over the entire surface of a wafer by assuming the decrease of an etching rate in the outer peripheral part of the wafer and previously thinly forming this outer peripheral part of the wafer prior to plasma etching processing of the entire surface of the wafer, a wafer planatarization system and the wafer. SOLUTION: A CMP apparatus 1 and a plasma etching apparatus 2 are provided. First, the outer peripheral part Wb of the wafer W held by a carrier 11 is polished thinner than the inner part Wc of the wafer W by the CMP apparatus 1 having a surface plate 10 of which the surface is formed to a recessed shape. More specifically, the wafer is so polished that the max. thickness in the outer peripheral part Wb of the wafer W is smaller than the min. thickness in the inner part Wc. The surface Wa of the wafer W is thereafter locally etched in the plasma etching apparatus 2, by which the wafer W of the high flatness free of a build-up in the outer peripheral part Wb is obtd.
申请公布号 JPH11302878(A) 申请公布日期 1999.11.02
申请号 JP19980126681 申请日期 1998.04.21
申请人 SPEEDFAM-IPEC CO LTD;HORIIKE YASUHIRO 发明人 TANAKA CHIKAU;YANAGISAWA MICHIHIKO;IIDA SHINYA;HORIIKE YASUHIRO
分类号 C23F4/00;H01L21/304;H01L21/306 主分类号 C23F4/00
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