| 摘要 |
PURPOSE:To improve a processing speed by providing a DMA controller formed in an information processor for executing binary format data transfer with a circuit converting an ASCII code into a binary format. CONSTITUTION:What data are sent from an information processor to an I/O device 12 in the information processor 1, the device 12 sends a signal DREQ to the DMA controller 1. The controller 11 sends a signal HRQ to a CPU14. When a signal HLDA is returned from the CPU 14, the controller 11 sends a signal RD to the device 12. Data sent from the device 12 are stored in a register 113a. Reference data are stored in a register 113b. When the contents stored in the registers 113a, 113b coincide with each other, the contents of the register 113a are sent to a converter circuit 111a for converting an ASCII code into a binary format. Since data transfer is executed by using the converted data, the processing speed can be improved. |
