发明名称 TRANSMISSION CIRCUIT AND RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform high-speed information transmission by serial signals provided with a low bit transition probability between semiconductor integrated circuits for handling parallel signals in respective internal parts. SOLUTION: Image data are transmitted from a memory 200 to a CPU 300. This transmission circuit 10 of the memory 200 receives the source parallel signals P of 8 bits, refers to transmission history or transmission prediction, generates the coded parallel signals ('00' in the case that P is invariable) of 2 bits from the source parallel signals P and transmits the serial signals S obtained by converting the coded parallel signals together with flag signals F for indicating coding presence. This reception circuit 110 of the CPU 300 receives the serial signals S and the flag signals F and restores the source parallel signals P of 8 bits based on reception history or reception prediction. In the case that the transmission circuit 10 fails in coding, the serial signals S obtained by converting the source parallel signals P themselves are transmitted together with the flag signals F for indicating coding absence.
申请公布号 JPH11298334(A) 申请公布日期 1999.10.29
申请号 JP19990024515 申请日期 1999.02.02
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAUCHI HIROYUKI
分类号 G06F5/00;H03M9/00;(IPC1-7):H03M9/00 主分类号 G06F5/00
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