发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To increase a defect saving efficiency and a product yield of a dynamic RAM of a layered IO system. SOLUTION: In a dynamic RAM of a layered IO system, sub-IO lines SI00* and SI10 have double the wiring length of, for example, the length of a memory array in the direction of a column and are shared between two memory mats, that is, memory arrays MARY00, MARY01 which are adjacent to each other in the direction of the column, and each of these memory arrays' has two sets of redundant bit lines RB0* and RB1* and RB2* and RB3", and is shared between two memory mats sharing the sub-TO lines SI00* and SI10. Or, a sub-IO line has half the wiring length of the length of the memory array in the direction of the column and, for example, redundant bit lines are gathered at one of q memory mats adjacently arranged in the direction of the column and are shared between the q adjacent memory mats.
申请公布号 JPH11297962(A) 申请公布日期 1999.10.29
申请号 JP19980112797 申请日期 1998.04.08
申请人 HITACHI LTD 发明人 NARUI SEIJI;HORIGUCHI SHINJI;FUJISAWA HIROKI;KAJITANI KAZUHIKO
分类号 G11C11/401;G11C29/00;G11C29/04;H01L21/8242;H01L27/108 主分类号 G11C11/401
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