REAL TIME DEBUGGER INTERFACE FOR EMBEDDED SYSTEMS

摘要

A debugging interface (10) includes a pair of decoders (28a, 28b) and an event history buffer (14) coupled to the sequencer of a processor. The first decoder is coupled to the instruction RAM of the processor. The second decoder (32a) is coupled to the cause register (22a) of the sequencer and the event history buffer (14) is also coupled to the cause register (22a). The first decoder (28a) provides a three bit real time output (30a) which is indicative of the processor activity on a cycle by cycle basis. The three bit output (30a) indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register. The event history buffer (14) is loaded with more detailed information about the instruction last executed when the first decoder (28a) indicates that the last instruction was an exception or a jump to a register, and when there is a change in state of an interrupt line or an internal processor exception.