An ATM cell processor (10) has a backplane interface (11), a line interface (15), and various processing functions between the interfaces. Cells directed to the line interface (15) are controlled by a queueing function (12) which uses external cell memory via a controller (13) and external control memory via a controller (14). Cells from the backplane are identified and routed by a mapping function (16).
申请公布号
WO9931928(A3)
申请公布日期
1999.10.28
申请号
WO1998IE00106
申请日期
1998.12.15
申请人
TELLABS RESEARCH LIMITED;DEWAR, KEVIN;O'DOWD, BRENDAN;BREBNER, GAVIN