Timing circuits are known and can be used to synchronize different circuits to each other. To obtain this, timing circuits with delay means delay an input signal with a predetermined value. To improve the known timing circuit the timing circuit of the invention comprises adjustable delay means, and further uses counting means to count the input signal and the output signal. In this way a simple and more cost effective timing circuit is obtained.
申请公布号
WO9955002(A1)
申请公布日期
1999.10.28
申请号
WO1999IB00664
申请日期
1999.04.15
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;PHILIPS AB
发明人
VAN ASMA, CORNELIS, G., M.;LAMMERS, MATHEUS, J., G.