| 摘要 |
A time-shared multitask execution circuit for sharing registered digital hardware among a plurality of users is provided to achieve zero overhead switching while processing as few as one sample in one clock cycle for each user. The circuit comprises a three register bank (10, 20, 30), two switches (40, 50), and a dual port RAM (60). On one given cycle, one register is processing data of a current user, one register is writing processed data of a prior user to the RAM (60), and one register is reading of a subsequent user for processing from the RAM (60). Therefore, processing, reading and writing are decoupled and proceed in parallel.
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