| 摘要 |
<p>A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches (151) within a Configuration Register (150). The Configuration Register (150) is included within the JTAG structure as a Test Data Register (TDR) (180). Each configuration bit within the Configuration Register (150) consists of a Configuration Latch (151), and each configuration latch (151) has an output used as a configuration control signal (160) within an output logic macrocell. The configuration register's input signal (149) is selectively provided from either a set of serially connected configuration bit non-volatile element sense latches (120) or from the JTAG Test Data In (TDI) data pin (101) for configuration, prototyping, and testing.</p> |
