发明名称 NONVOLATILE SEMICONDUCTOR MEMORY AND TEST METHOD THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory and test method thereof whereby the failure analyzing time can be reduced and yield can be improved by detecting memory cells being in the deplete state. SOLUTION: The test method is such that a high threshold state of a memory cell corresponds to an erase state, a low threshold state of the memory cell corresponds to a date write state, the sources of a plurality of memory cells are connected to a common source line provided with a voltage switching means for feeding a higher voltage e.g. 1 V than at the data read in a deplete test to the common source line, applying a lower voltage e.g. 1.5 V than at the data read to a not selected word line of 0 V to a selected word line, and precharging bit lines to a higher potential e.g. 2 V than at the data read.</p>
申请公布号 JPH11297100(A) 申请公布日期 1999.10.29
申请号 JP19980091093 申请日期 1998.04.03
申请人 HITACHI LTD 发明人 HONDA HIDENORI;SATO HIROSHI
分类号 G01R31/28;G11C16/06;G11C29/00;G11C29/12;(IPC1-7):G11C29/00 主分类号 G01R31/28
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