| 摘要 |
1448041 Data processor STANDARD TELEPHONES & CABLES Ltd 23 May 1974 23067/74 Heading G4A A data processor includes inputs connected to respective input staticizers, outputs connected to respective output staticizers, a random access memory arranged to store intermediate processing results, an input arranged to receive instructions having function and address parts, and a logic unit arranged to process one bit operands from the input staticizers and/or the random access memory to produce one bit results which are directed to an output staticizer or the random access memory, the operand source and result destinations being selected by the address parts of instructions whose function parts determine the operations to be performed, e.g. read, write, AND, OR. The processor may be used to interface controlled equipment, e.g. a telephone exchange, and a controlling digital computer and may be formed on a single integrated circuit chip. One or more of the processors may be supplied with instructions from an external read only program memory. Several such program memories storing respective programs may be provided, a selected one being supplied with clock pulses. In a first embodiment the input staticizers, output staticizers, and the random access memory are connected, together with a number of delay units formed by shift registers to internal input and output buses. All the units, input staticizer delays &c., together with various clock pulse sources are addressed by the address part of an instruction and the buses are connected to a push down stack. The processor performs AND and OR operations between the contents of the top two stack locations and loads the result into the top location. The result may also be transferred to any unit, e.g. output staticizer, addressed by the current instruction, or may be retained in the stack. In a second embodiment, Fig. 3, the random access memory RAM, delays DEL, and input and output staticizers IS, OS are connected to the logic unit via selectors WAS, RAS activated by the address part of an instruction ADO, the logic unit being controlled by the function part FO. The logic unit, Fig. 4, consists of two NAND gates N1, N2, each formed by an AND gate and a bi-stable, which NANDs successive operands. The instruction format allows the outputs of both NANDs to be connected to the input of the other NAND or to addressed units in the processor, output staticizers &c., and the Specification gives details of the way in which Boolean functions can be evaluated. Additional external random access memories may be coupled to the processor. |
