发明名称 METHOD FOR CACHEING CONFIGURATION DATA OF DATA FLOW PROCESSORS AND MODULES WITH A TWO- OR MULTIDIMENSIONAL PROGRAMMABLE CELL STRUCTURE (FPGAs, DPGAs OR SIMILAR) ACCORDING TO A HIERARCHY
摘要 Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. The tree structure of the configuration units enables a kind of cacheing of the configuration data. The configurations are mainly accessed locally. In the worst case scenario, a configuration has to be loaded from the higher-order configuration memory in case the relative data are not available in any of the CTs (configuration tables) in the hierarchy.
申请公布号 WO9944147(A3) 申请公布日期 1999.10.28
申请号 WO1999DE00504 申请日期 1999.02.25
申请人 PACT INFORMATIONSTECHNOLOGIE GMBH;VORBACH, MARTIN;MUENCH, ROBERT 发明人 VORBACH, MARTIN;MUENCH, ROBERT
分类号 G06F12/08;G06F15/78;G06F15/82;H03K19/173 主分类号 G06F12/08
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