发明名称 INTER-PROCESSOR COMMUNICATION PROTOCOL
摘要 : Processors of a multiprocessor system communicate across bus via a low-latency packet protocol featuring per-logical channel input queues and output queues, different perprocessor priorities for sending data packets and data packetacknowledging "quick" messages, and separate buffers for receiving data packets and "quick" messages, respectively. Transmitted data packets afflicted by error, receive buffer overflow, and input queue-full conditions are discarded by the receiving processor and are retransmitted by the sending processor.
申请公布号 CA1277382(C) 申请公布日期 1990.12.04
申请号 CA19870554812 申请日期 1987.12.18
申请人 BISHOP, THOMAS P. 发明人 BISHOP, THOMAS P.;DAVIS, MARK H.;HORN, DAVID N.;SURRATT, GROVER T.;WELSCH, LAWRENCE A.
分类号 G06F15/16;G06F9/46;G06F11/14;G06F13/00;G06F13/374;G06F13/42;G06F15/177;H04L12/56;H04L29/00 主分类号 G06F15/16
代理机构 代理人
主权项
地址